AC2 Software interface

Board identification (base address + 15)

This read-only register returns the value 0CH if the board is in 8-bit mode or 0BH if the board is in 16-bit mode.

Status register (base register + 14)

This read-only register returns the status of the AC2 card. Status bits are as follows:

Bit 7

Not used.

Bit 6 - BUSY

This bit is set to “1” when the AC2 has been commanded to acquire data. It is reset to “0” when the data conversion is complete. This takes approximately 15 μs.

NOTE: The host PC should not attempt to read the probe deflections or the timer value while the BUSY bit is set to “1”. Any data read during this period will be invalid.

Bit 5 - TIMER OVERFLOW

This bit is set to “1” when the timer has overflowed. It is reset to “0” when the timer has been reset.

Bit 4 - PROBE PRESENT

This bit is set to “1” if an SP600/M/Q probe has been connected to the AC2 and the REQUEST SET PROBE PRESENT bit has been written to with a “1” (see "Detection of a connected SP600/M/Q section"). If the probe is disconnected from the AC2, then the bit automatically resets to “0”.

Bit 3 - OVERTRAVEL ERROR

This bit is set to “1” if the overtravel unit is overtravelled or not connected. It is set to zero if the overtravel unit is connected, not overtravelled, and the REQUEST RESET OVERTRAVEL bit has been written to with a “1” (see “Interface for the SP60 overtravel unit”).

Bit 2, 1, 0 - OVERCURRENT STATUS FLAGS

These show the status of the three probe output overcurrent protection devices on the AC2. They are set to “1” when one of the probe supplies has had an overcurrent.

AC2 I/O map

Register name

Base address offset

Bit reference

 Data

 Read/write

X axis LO byte

0

7 to 0

 2’s complement 12 bit count 8000H to 7FFFH

Read only

X axis HI byte

1

15 to 8

 2’s complement 12 bit count 8000H to 7FFFH

Read only

Y axis LO byte

2

7 to 0

 2’s complement 12 bit count 8000H to 7FFFH

Read only

Y axis high byte

3

15 to 8

 2’s complement 12 bit count 8000H to 7FFFH

Read only

Z axis LO byte

4

7 to 0

 2’s complement 12 bit count 8000H to 7FFFH

Read only

Z axis HI byte

5

15 to 8

 2’s complement 12 bit count 8000H to 7FFFH

Read only

Timer LO count

6

7 to 0

 16 bit binary count 0000H to FFFFH

Read only

Timer HI count

7

15 to 8

 16 bit binary count 0000H to FFFFH

Read only

Page selection

8

N/A

 Selects pages 0, 1 or 2

N/A

Not used

9

15 to 8

 Reads back 00H

Read only

PICS & interrupt status

10

7 to 0

Bits are set if the condition is true

Read only

Not used

11

15 to 8

Reads back 00H

Read only

Acquisition mode selected

12

7 to 0

Set the bit to command the function

Read/write

Command register

13

15 to 8

Write “1” to the relevant bit to activate

Write only

Status register

14

7 to 0

Bits set to logic 1 if condition true

Read only

AC2 board identification

15

15 to 8

Page 0 returns the value “0BH” or “0CH

Read only

PICS & interrupt status register definitions

7

Not used (set to logic 1)

6

Not used (set to logic 1)

5

Not used (set to logic 1)

4

Not used (set to logic 1)

3

PICS READ

2

PICS PDAMP

1

PICS PPOFF

0

Interrupt requested

 

Command register definitions

7

Not used (set to logic 0)

6

BUSY

5

TIMER OVERFLOW

4

PROBE PRESENT

3

OVERTRAVEL

2

5 V OVERCURRENT

1

-12 V OVERCURRENT

0

+12 V OVERCURRENT

 

Acquisition mode register definitions

7

Interrupt line select bit 2

6

Interrupt line select bit 1

5

Interrupt line select bit 0

4

Level/shared interrupt mode selection

3

Not used

2

Acquisition mode select bit 2

1

Acquisition mode select bit 1 (see table on page 71)

0

Acquisition mode select bit 0

 

Command register definitions

15

Not used

14

Not used

13

Not used

12

Not used

11

ACQUIRE data and latch timer count (sets BUSY true until complete)

10

REQUEST SET PROBE PRESENT

9

REQUEST RESET OVERTRAVEL

8

RESET TIMER

Command register (base address + 13)

This write-only register allows the software to control the AC2.  Functions are commanded by writing a “1” to the appropriate bit.  When a “0” is written to a bit, nothing happens. This allows the
software to control individual functions by writing to selected bits with a “1”, while leaving the other bits set to “0”.

The command bits are shown below:

Bits 15 to 12

Not used 

Bit 11 - ACQUIRE data and latch timer count

Writing a “1” to this bit causes the AC2 to acquire the SP600 axis deflections and latch the time stamp. The data is presented in registers “5” to “0”, and the time stamp is latched into registers “7” and “6”. While the data acquisitions process takes place, its progress can be monitored by inspecting the BUSY bit in the status register. Writing a “1” to this bit can take place in any of the AC2 operating modes and will result in data acquisition.

Bit 10 - REQUEST SET PROBE PRESENT

Writing a “1” to this bit causes the AC2 to sample the state of its probe identification circuitry. Upon writing to this bit, the PROBE PRESENT bit in the status register is set to “1” if an SP600/M/Q probe is present.

Bit 9 - REQUEST RESET OVERTRAVEL

Writing “1” to this bit causes the AC2 to sample the state of its overtravel circuitry. Upon writing to this bit, the OVERTRAVEL bit in the status register is set to “0” if an overtravel unit is connected and not overtravelled.

Bit 8 - RESET TIMER

Writing a “1” to this bit causes the AC2 to reset the AC2 timer to 0000H and resets the TIMER OVERFLOW flag to “0”.

Acquisition mode select register (base address + 12)

This read/write register allows the software to set the AC2 to the required acquisition mode, with a selected interrupt (if required).

The command bits are shown below:

Bits 7 to 5 - INTERRUPT SELECTION

Writing the data pattern shown in the table below will select the interrupt shown in the table. Interrupts are valid in acquisition modes 3, 4 and 5. Upon power up, IRQ3 is selected.

Interrupt request line

 Selection interrupt line bit 765

 IRQ

 IBM ISA bus definition

 000

 IRQ3

 Serial port 2

 001

 IRQ5

 Parallel port 2

 010

 IRQ7

 Parallel port 1

 011

 IRQ9

 Software

 100

 IRQ10

 Reserved

 101

 IRQ11

 Reserved

 110

 IRQ12

 Reserved

 111

 IRQ15

 Reserved

Bit 4 - SHARED/LEVEL INTERRUPT MODE SELECTION

Writing a “1” to this bit enables shared interrupt mode. Writing a “0”, enables level interrupt mode. Upon power up, level interrupt mode is selected.

Bit 3

Not used

Bits 2 to 0 - ACQUISITION MODE

Writing the data pattern shown in the table below will select the acquisition mode in the table. Upon power up, mode 0 is selected, causing the AC2 to emulate an AC1.

Acquisition mode bit select

 Acquisition mode bit 210

 Mode

Mode type

 000

 0

 ISA bus acquire without PICS SYNC (default)

 001

 1

 ISA bus acquire with PICS SYNC and HALT

 010

 2

 PICS READ without interrupt

 011

3

 PICS READ with interrupt

 100

 4

 Reversed direction interrupt without PICS SYNC

 101

5

 Reversed direction interrupt with PICS SYNC

 110

0

 ISA bus acquire without PICS SYNC (default)

 111

0

 ISA bus acquire without PICS SYNC (default)

 

DATA ACQUISITION MODES

The AC2 has six modes for acquiring measurement data. These are described below:

Mode 0

This is the default mode of operation after power has been applied to the AC2 or a system reset has occurred. AC2 does not respond to the PICS READ command, or reversed direction interrupt, nor generate PICS SYNC or any interrupt. When the user writes a “1” to bit “11” of the command register (“base +13”) the timer value is latched, the BUSY bit is set and the conversation of the three measurement channels begins. When the data from the measurement channels is available to be read over the ISA bus, the BUSY fl ag is lowered and the AC2 is ready for another conversation.

Mode 1 ISA bus acquire with PICS SYNC

This mode is identical to mode 0 with additional activity on the PICS interface. During the period that the BUSY bit is set, PICS SYNC is set to its active state.

Mode 2 PICS READ without interrupt

In this mode the AC2 responds as in mode 0 when to bit “11” of the command register is written to with a “1”. In addition, on the falling edge of the PICS READ signal, the timer value is latched, the BUSY bit is set and the conversation of the three measurement channels begin. The BUSY bit is lowered in the same way as for mode 0.

Mode 3 PICS READ with interrupt

This is identical to mode 2, except that when the BUSY bit is lowered at the end of the data acquisition, the interrupt selected by bits “7”, “6”, “5” and “4” of the acquisition mode selection register becomes active.  The interrupt is cleared by reading any AC2 register. This feature has
been included so that customers who do not want to bother resetting the interrupt bit can just read the measurement register.

It is essential that any user who wants to read the interrupt bit at address “base +10”, reads this address fi rst after the interrupt has occurred. If the user does not, the interrupt will be cleared and the bit in the status register will be reset to “0” before the software has read it.

Mode 4 Reversed direction interrupt without PICS SYNC (used by some CMM controllers)

In this mode the AC2 responds as in mode 0 when to bit “11” of the command register is written to with a “1”. In addition, when the AC2 sees a rising edge on the interrupt selected by bits “7”, “6” and “5” of the acquisition mode selection register, the timer value is latched, the BUSY bit is set and the conversion of the three measurement channels begins. The BUSY bit is lowered in the same way as for mode 0. A second conversion will not occur until after the selected interrupt has gone to logic “0” again. Bit “4” of the acquisition mode register is ignored.

Mode 5 Reversed direction interrupt with PICS SYNC

This is identical to mode 4 with additional activity on the PICS interface. During the period that the BUSY bit is set, PICS SYNC is set to its active state for the duration of the BUSY period.

Using INTERRUPTS

The AC2 can use any of the following interrupts: IRQ3, IRQ5, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12 and IRQ15. These are selected by bits “7”, “6” and “5” of the acquisition mode select register. An interrupt is only generated when acquisition mode 3 is selected. 

One of two interrupt methods is selected by bit “4” of the acquisition mode select register. When previously written with a “1”, shared interrupt operation will occur. The host PC (bus master) holds the
interrupt line high with a passive pull up resistor. When the AC2 requests an interrupt it generates an active low pulse on the interrupt line selected using a driver that generates an active low or high impedance output. This pulse lasts for approximately 500 ns. The bus master determines that the AC2 is the source of the interrupt by polling the PICS and interrupt status register.

 

NOTE: Reading any of the AC2 registers resets the interrupt bit, therefore it is essential that the polling routine reads this register only.

After power on or reset, or after a “0” is written to bit “4” of the acquisition mode select register, level interrupt operation will occur.  This is described in the IBM PC-AT technical reference manual. In
this mode, the AC2 drives the interrupt line to logic “0” when the interrupt mode has been selected. When an interrupt is needed, the AC2 asserts it by driving the selected interrupt line to logic “1”. The interrupt line returns to logic “0” and the interrupt bit is cleared when any register in the AC2 is read by the bus master.  All unselected interrupt lines present a high impedance to the ISA bus, except when the ΔT bus interface is selected. When this occurs, all interrupts will be set to logic “0”.

In either mode, after an interrupt has occurred, bit “0” of the PICS and interrupt status register is set. This bit is cleared by reading any register in the AC2.

INTERRUPT TESTING

Simulating the use of interrupts in both modes using the ACQUIRE bit of the command register described in section 4.3.4 is possible.  Writing “1” to this register causes the AC2 to respond as though it has received an interrupt signal when the AC2 has been set to acquisition Modes 4 and 5. It causes the acquisition of data and the generation of an interrupt when the AC2 has been set to acquisition mode 3.

PICS and interrupt status register (base address + 10)

This read only register returns the status of the AC2 card. The status bits are shown below:

Bits 7 to 4

Not used

Bit 3 - PICS READ

This bit is set to “1” when PICSREAD is asserted (pulled low) by a device connected to the PICS interface. It is reset to “0” when PICSREAD is unasserted.

Bit 2 - PICS PDAMP

This bit is set to “1” when PICSDAMP is asserted (pulled low) by a device connected to the PICS interface. It is reset to “0” when PICSDAMP is unasserted.

Bit 1 - PICS PPOFF

This bit is set to “1” when PICS PPOFF is asserted (pulled low) by a device connected to the PICS interface. It is reset to “0” when PICS PPOFF is unasserted.

Bit 0 - INTERRUPT

This bit is set to “1” when the AC2 asserts an interrupt in mode 3, or when the AC2 is receiving an interrupt in modes 4 and 5. It is reset to “0” when the selected interrupt is not asserted.

Page register (base address + 8)

Writing to this register selects the data that is presented at address base + 15”, shown below:

 

Base + 15

Contents

Page 0

IDENTITY BYTE “0CH” when 8 bit mode is selected or “0BH” when 16-bit mode is selected.

Page 1

HARDWARD VERSION NUMBER. This shows the version of the assembly drawing of the adaptor card.  Application software must read and present this number to the customer on request, but the software execution will not depend upon its value.

Page 2

FUNCTIONALITY REVISION NUMBER. This shows the version of the functionality of the adaptor card. This number will be incremented each time a change is made to the adaptor card that changes its functionality. For applications that are safely critical (e.g. motion control, cutting tool enabled, etc) the software must check that it is using a version of the adaptor card for which it was designed.

If the software does not contain a device driver for the version of the card, it must generate an error message and not attempt to operate the card.

 

CAUTION: If the FUNCTIONALITY REVISION NUMBER of the AC2 has changed, it is still the software designer’s responsibility to ensure that any existing software is still compatible with the new version of the AC2.

 

Timer count LO and HI bytes (base address +7 and +6)

These read-only registers return the latched LO and HI byte of the AC2 internal timer. The latched timer value is updated each time the axis is deflections are acquired.

NOTE: It is possible for the counter to have an offset of up to 1 μs from the time of writing to the RESET TIMER bit.

Axis deflection LO and HI bytes (base address +5 through to 0)

These read-only registers return the LO and HI byte of the X, Y and Z axis deflections of the probe. The format of these values is 2’s complement 16-bit counts which can take any value between 8000H and 7FFFH. The deflections are only updated when an appropriate hardware synchronisation is sent to the AC2 or the acquire bit is written to.