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AC3 I/O map
Register name | Base address offset | Bit reference | Data | Read / write |
|---|---|---|---|---|
'p' axis LO byte | 0 | 7 to 0 | 2's complement 16 bit count 8000H to 7FFFH | Read only |
'p' axis HI byte | 1 | 15 to 8 | 2's complement 16 bit count 8000H to 7FFFH | Read only |
'q' axis LO byte | 2 | 7 to 0 | 2's complement 16 bit count 8000H to 7FFFH | Read only |
'q' axis HI byte | 3 | 15 to 8 | 2's complement 16 bit count 8000H to 7FFFH | Read only |
'r' axis LO byte | 4 | 7 to 0 | 2's complement 16 bit count 8000H to 7FFFH | Read only |
'r' axis HI byte | 5 | 15 to 8 | 2's complement 16 bit count 8000H to 7FFFH | Read only |
Timer LO count | 6 | 7 to 0 | 16 bit binary count 0000H to FFFFH | Read only |
Timer HI count | 7 | 15 to 8 | 16 bit binary count 0000H to FFFFH | Read only |
Page selection | 8 | 7 to 0 | Selects pages 0, 1 or 2 | Read / write |
Not used | 9 | 15 to 8 | Reads back 00H | Read only |
PICS & interrupted status | 10 | 7 to 0 | Bits are set if the condition is true | Read only |
PICS & interrupt status register definitions: |
|
| 7 to 4 - Not used (logic set to 0) |
|
Not used | 11 | 15 to 8 | Reads back 00H | Read only |
Acquisition mode select | 12 | 7 to 0 | Set the bit to command the function | Read / write |
Register name | Base address offset | Bit reference | Data | Read / write |
|---|---|---|---|---|
| Acquisition mode register definitions: | 7 - Interrupt line select bit 2 (see table 14) | |||
Command register | 13 | 15 to 8 | Write 1' to the relevant bit to activate | Write only |
Command register definitions: |
|
| 15 - Not used |
|
Status register | 14 | 7 to 0 | Bits set to logic if condition TRUE | Read only |
Status register definitions: |
|
| 7 - Not used (set logic to 0) |
|
AC3 identification & functionality version | 15 | 15 to 8 | Page 0 returns the value 09H' or 0AH' | Read only |