Acquisition mode select register (base address + 12)

This read/write register allows the software to set the AC3 to the required acquisition mode, with a selected interrupt (if required). The command bits are shown below:

Bits 7 to 5 - INTERRUPT SELECTION

  • Writing the data pattern shown in table 6 will select the interrupt shown in the table. Interrupts are valid in acquisition modes 3, 4 and 5. Upon power up, IRQ3 is selected.

Selection interrupt
line bit 765

IRQ

IBM ISA bus definition

000

IRQ3

Serial port 2

001

IRQ5

Parallel port 2

010

IRQ7

Parallel port 1

011

IRQ9

Software

100

IRQ10

Reserved

101

IRQ11

Reserved

110

IRQ12

Reserved

111

IRQ15

Reserved

Bit 4 - SHARED/LEVEL INTERRUPT MODE SELECTION

  • Writing a ‘1' to this bit enables shared interrupt mode. Writing a ‘0' enables level interrupt mode. Upon power up, level interrupt mode is selected.

Bit 3 - This bit is not used.

Bits 2 to 0 - ACQUISITION MODE

  • Writing the data pattern shown in the table below will select the acquisition mode in the table. Upon power up, mode 0 is selected.

Acquisition
mode bit 210

Mode

Mode type

000

0

ISA bus acquire without PICS SYNC (default)

001

1

ISA bus acquire with PICS SYNC and HALT

010

2

PICS READ without interrupt

011

3

PICS READ with interrupt

100

4

Reversed direction interrupt without PICS SYNC

101

5

Reversed direction interrupt with PICS SYNC

110

0

ISA bus acquire without PICS SYNC (default)

111

0

ISA bus acquire with PICS SYNC and HALT