AC2 software interface

Command register (base address + 13)

This write-only register allows the software to control the AC2. Functions are commanded by writing a “1” to the appropriate bit. When a “0” is written to a bit, nothing happens. This allows the
software to control individual functions by writing to selected bits with a “1”, while leaving the other bits set to “0”.

The command bits are shown below:

Bits 15 to 12

Not used

Bit 11 - ACQUIRE data and latch timer count

Writing a “1” to this bit causes the AC2 to acquire the SP600 axis deflections and latch the time stamp. The data is presented in registers “5” to “0”, and the time stamp is latched into registers “7” and “6”. While the data acquisitions process takes place, its progress can be monitored by inspecting the BUSY bit in the status register. Writing a “1” to this bit can take place in any of the AC2 operating modes and will result in data acquisition.

Bit 10 - REQUEST SET PROBE PRESENT

Writing a “1” to this bit causes the AC2 to sample the state of its probe identification circuitry. Upon writing to this bit, the PROBE PRESENT bit in the status register is set to “1” if an SP600/M/Q probe is present.

Bit 9 - REQUEST RESET OVERTRAVEL

Writing “1” to this bit causes the AC2 to sample the state of its overtravel circuitry. Upon writing to this bit, the OVERTRAVEL bit in the status register is set to “0” if an overtravel unit is connected and not overtravelled.

Bit 8 - RESET TIMER

Writing a “1” to this bit causes the AC2 to reset the AC2 timer to 0000H and resets the TIMER OVERFLOW flag to “0”.

DATA ACQUISITION MODES

The AC2 has six modes for acquiring measurement data. These are described below:

Mode 0

This is the default mode of operation after power has been applied to the AC2 or a system reset has occurred. AC2 does not respond to the PICS READ command, or reversed direction interrupt, nor generate PICS SYNC or any interrupt. When the user writes a “1” to bit “11” of the command register (“base +13”) the timer value is latched, the BUSY bit is set and the conversation of the three measurement channels begins. When the data from the measurement channels is available to be read over the ISA bus, the BUSY flag is lowered and the AC2 is ready for another conversation.

Mode 1 ISA bus acquire with PICS SYNC

This mode is identical to mode 0 with additional activity on the PICS interface. During the period that the BUSY bit is set, PICS SYNC is set to its active state.

Mode 2 PICS READ without interrupt

In this mode the AC2 responds as in mode 0 when to bit “11” of the command register is written to with a “1”. In addition, on the falling edge of the PICS READ signal, the timer value is latched, the BUSY bit is set and the conversation of the three measurement channels begins. The BUSY bit is lowered in the same way as for mode 0.

Mode 3 PICS READ with interrupt

This is identical to mode 2, except that when the BUSY bit is lowered at the end of the data acquisition, the interrupt selected by bits “7”, “6”, “5” and “4” of the acquisition mode selection register becomes active. The interrupt is cleared by reading any AC2 register. This feature has been included so that customers who do not want to bother resetting the interrupt bit can just read the measurement register.

It is essential that any user who wants to read the interrupt bit at address “base +10”, reads this address first after the interrupt has occurred. If the user does not, the interrupt will be cleared and the bit in the status register will be reset to “0” before the software has read it.

Mode 4 Reversed direction interrupt without PICS SYNC (used by some CMM controllers)

In this mode the AC2 responds as in mode 0 when to bit “11” of the command register is written to with a “1”. In addition, when the AC2 sees a rising edge on the interrupt selected by bits “7”, “6” and “5” of the acquisition mode selection register, the timer value is latched, the BUSY bit is set and the conversion of the three measurement channels begins. The BUSY bit is lowered in the same way as for mode 0. A second conversion will not occur until after the selected interrupt has gone to logic “0” again. Bit “4” of the acquisition mode register is ignored.

Mode 5 Reversed direction interrupt with PICS SYNC

This is identical to mode 4 with additional activity on the PICS interface. During the period that the BUSY bit is set, PICS SYNC is set to its active state for the duration of the BUSY period.

Using INTERRUPTS

The AC2 can use any of the following interrupts: IRQ3, IRQ5, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12 and IRQ15. These are selected by bits “7”, “6” and “5” of the acquisition mode select register. An interrupt is only generated when acquisition mode 3 is selected.

One of two interrupt methods is selected by bit “4” of the acquisition mode select register. When previously written with a “1”, shared interrupt operation will occur. The host PC (bus master) holds the interrupt line high with a passive pull up resistor. When the AC2 requests an interrupt it generates an active low pulse on the interrupt line selected using a driver that generates an active low or high impedance output. This pulse lasts for approximately 500 ns. The bus master determines that the AC2 is the source of the interrupt by polling the PICS and interrupt status register.